Accurate modeling of semiconductor devices is needed to provide reliable circuit simulation results that can predict the behavior of an ultra-large-scale-integration (ULSI) semiconductor circuit. Typically, a ULSI semiconductor circuit includes more than 100,000 transistors, and a large scale circuit simulation is required to verify functionality of the ULSI semiconductor circuit. Often, such circuit simulations are used during a design phase of a circuit to predict circuit characteristics such as the drive current of an individual circuit component, the signal delay between multiple circuit components, or the overall performance of a circuit in terms of the operating speed of a chip and interaction with other chips.
Models for circuit design are referred to as compact models, which include analytical compact models and approximate models. An analytical compact model employs an extensive array of circuit parameters to provide an accurate model for a semiconductor device. While accuracy of a circuit simulation employing an analytical compact model tends to be high, such simulations typically require a long run time. In addition, further refinement of the analytical compact model to account for additional layout dependency of circuit parameters may increase the complexity of the analytical compact model and the run time beyond a manageable level.
In contrast, approximate models employ less parameters for simulation. Approximate models include table-based approximate models and switch-level approximate models. A table-based approximate model provides values for various circuit elements based on layout parameters. The circuit elements may include current sources, inductors, charge elements such as a capacitor, etc. The table-based approximate model employs predefined tables to calculate such circuit elements, and as a consequence, tends to be much simpler than analytical compact models and requires a shorter run time. A switch-level approximate model provides a high level circuit simulation through a set of formulae that describes a time-dependant response of the semiconductor circuit. The switch-level approximate model may provide an accurate simulation result in a shorter run time than analytical compact models.
Recently, various layout-dependant effects have been known in the semiconductor technology including effects of engineered stress, effects of local reflectivity on temperature during rapid thermal anneals, and lithographic effects on the physical shape of contact level (CA) vias and subsequent electrical impacts. Such layout-dependant effects on a semiconductor device depend on many parameters of adjacent semiconductor devices. Consequently, attempts to incorporate the layout-dependent effects into an analytical compact model typically result in an inordinate increase in complexity and run time, rendering such incorporation impractical.
Incorporation of the layout-dependant effects into an approximate model faces similar challenges. Expanding entries of a table file in a table-based approximate model to account for layout-dependant effects increases the dimension of the table file for each layout-dependant effect to be accounted for. As the table file becomes larger and more complex, generation time for the table file increases, and more operations are required to search the table, contributing to an increase in overall run time. Thus, incorporation of the layout-dependant effects into the table-based approximate model can make the run time of a simulation unmanageable.
Likewise, modification of a switch-level approximate model to incorporate layout dependant effects also requires extensive modification to the formulae for time-dependant responses to include the effects of the elements that cause the layout-dependant effects, thereby increasing the run time beyond a manageable level.
In view of the above, there exists a need for methodology for accurately reflecting layout-dependant effects in a circuit simulation result without requiring an excessive run time, and a system including a model for effecting the same.